1. Field of the Invention
This invention relates to a layout of a semiconductor integrated circuit using a capacitor, particularly to reduction of parasitic capacitance due to leader wirings from the capacitor.
2. Description of the Prior Art
In a capacitor for use in a switched capacitor circuit (hereinafter referred to as a SC circuit) and the like which are widely used in an analog LSI, an analog-digital mixed loading LSI or the like, a high specific accuracy in capacitance ratio is required. This is for the reason that, for example, in a circuit gain of the SC circuit is set by the ratio of capacitance to capacitance. In designing such capacitor, it is considered that the specific accuracy is ensured by generally using unit capacitors each having a unit capacitance C.sub.o and, for example, in the case that the capacitance of three times the unit capacitor C.sub.o is necessary, connecting the three unit capacitor C.sub.o in parallel. In this case, the layout is as shown, for example, in FIG. 1. Namely, lower electrodes 10 and 11 are formed on a semiconductor wafer substrate through an insulating film, upper electrodes 12-15 having a unit area are formed thereon through a dielectric film, the lower electrodes 11 and 10 are connected with aluminum wirings 6 and 16, respectively, the upper electrode 12 is connected with aluminum wiring 5 and furthermore the upper electrodes 13-15 are connected with aluminum wiring 17.
In case of the capacitor in which such specific accuracy is required, generally both of the upper electrodes 12-15 and the lower electrodes 10 and 11 are mostly formed with polycrystal silicon. This is for the reason that a bias dependency of the capacitance is lost by forming the upper and lower electrodes 10-15 with the same material. The upper electrodes 12-15 and the lower electrodes 10 and 11 are connected with the required circuit through the leader wirings 5, 6, 16 and 17 which were made from a wiring material such as aluminum or the like. In the portion in which the wiring material such as aluminum or the like is densely laid out, the leader wirings 5 and 17 from the upper electrodes 12 and 13-15, respectively, and the leader wirings 16 and 6 from the lower electrodes 10 and 11, respectively, are proximately arranged in many cases as in a region A of FIG. 1. FIG. 2 shows a sectional view taken along the face B--B' of the region A. As shown in FIG. 2, the leader wirings 5 and 6 of aluminum are formed above the semiconductor substrate 1 through a silicon oxide film 2 and an interlayer insulating film 3, and further an interlayer insulating film 4 and a covering film 8 are formed thereon. In this case, the line of electric force spreads out as shown in FIG. 2 and the capacitance between the wirings increases by about 1.5 times the capacitance as calculated supporting that the wiring materials 5 and 6 are in the form of plane parallel plates.
In the case that the leader wirings were proximately arranged as mentioned above, there was a defect that the parasitic capacitance between the wirings is added to the unit capacitance C.sub.o and thus the specific accuracy of capacitance or capacitance ratio becomes worse. Of course, if the leader wirings are not laid in close proximity to each other, the above problem is not serious. In this case, however, the layout is remarkably restricted and the layout area increases.